RESET_PIN_CFG=00, FAST_INIT=00, LPBOOT1=00, NMI_DIS=00, LPBOOT0=00
Non-volatile Flash Option Register
LPBOOT0 | no description available 0 (00): Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. 1 (01): Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. |
NMI_DIS | no description available 0 (00): NMI interrupts are always blocked 1 (01): NMI_b pin/interrupts reset default to enabled |
RESET_PIN_CFG | no description available 0 (00): RESET pin is disabled following a POR and cannot be enabled as reset function 1 (01): RESET_b pin is dedicated |
LPBOOT1 | no description available 0 (00): Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. 1 (01): Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. |
FAST_INIT | no description available 0 (00): Slower initialization 1 (01): Fast Initialization |